ARM64/AArch64 Assembly Cheat Sheet

Registers

Register	Low 32-bits	Calling convention
General-purpose registers:
x0	w0
x1	w1
x2	w2
Special-purpose registers:
xzr	wzr	Zero register
sp	-	Stack pointer

Data type

Definition size	Definition instruction
8 bit	byte
16 bit	hword
32 bit	word
64 bit	dword

Load from immediate

movz/mov + movk

Load the 64-bit integer 0x1a2b3c4d1a2b3c4d from the immediate,

// Load the 64-bit integer `0x1a2b3c4d1a2b3c4d` from the immediate
movz     x1, #0x3c4d
movk    x1, #0x1a2b, lsl #16
movk    x1, #0x3c4d, lsl #32
movk    x1, #0x1a2b, lsl #48

Load from label

Load instruction	Purpose
ldr x0, [x1]	load 64-bit
ldr w0, [x1]	load 32-bit
ldrh w0, [x1]	load 16-bit
ldrb w0, [x1]	load 8-bit

Assume the 32-bit data in .data section,

.data
    int32_var:  .word   0x1a2b3c4d

adr: shift by byte(±1M, one instruction), the assembler will do:

• calculate the PC-relative offset from the current adr instruction to the label int32_var in bytes.
• encode the offset in the adr instruction.

adr	    x20, int32_var
ldr     x2, [x20]

adrp + add: shift by 4KB page(±4G, two instructions), the assembler will do:

• calculate the PC-relative offset from the current adr instruction to the label int32_var in page.
  • calculate the PC-relative offset in bytes.
  • divide the byte offset using 4096(or right shift 12 bits), now the quotient is page offset
• encode the page offset in the adrp instruction.
• encode the lower 12 bits in the add instruction.

adrp	x20, int32_var
add     x20, x20, :lo12:int32_var
ldr    x2, [x20]

or more simply,

adrp	x20, int32_var
ldr    x2, [x20, :lo12:int32_var]

in macOS m1,

adrp	x20, int32_var@PAGE
add     x20, x20, int32_var@PAGEOFF
ldr    x2, [x20]

Store

Resources

ios-resources/bits/arm64.md at master · Siguza/ios-resources · GitHub

asm_book/section_1/regs/ldr.md at main · pkivolowitz/asm_book · GitHub

Exploring AArch64 assembler – Chapter 5

https://peterdn.com/post/2020/08/22/hello-world-in-arm64-assembly/

https://gpanders.com/blog/exploring-mach-o-part-1/

https://iitd-plos.github.io/col718/ref/arm-instructionset.pdf

https://modexp.wordpress.com/2018/10/30/arm64-assembly/#registers

https://stackoverflow.com/questions/41906688/what-are-the-semantics-of-adrp-and-adrl-instructions-in-arm-assembly